Designing a Transceiver-based Application with Vitis

The Xilinx® Vitis™ unified software platform enables the development of embedded software and accelerated applications on heterogeneous Xilinx platforms including FPGAs, SoCs, and Versal ACAPs.

For transceiver applications, hardware designers typically adopt RTL and IPI design methodology in Vivado. This article studies how Vitis technology can be used to create GT-based IP designs.

In the Vitis software platform, a GT-based IP shell design can be generated, and it also provides a kernel service through which a user can generate/port custom patterns with simple C code. Other GT-based IP features can also be ported to a Vitis-based system as well.

Vitis technology provides a unified methodology for hardware and software engineering to collaborate in the design and validation process: Emulate-HW, Emulate-SW and System builds and tests.

Below is an example kernel based on an Alveo U200 Data Center accelerator card. This shell example illustrates two RTL kernels (the dynamic region). The size of the dynamic region depends on the PL resources used, including LUTs, DSPs, IOs, and memory. AXI interfaces are deployed for data transfer between RTL kernels, local memory subsystem, and host memory. The static region is platform-dependent and provides a gateway to the host system and host memory.

Based on the above U200 XDMA Alveo platform, a simple GT Kernel platform architecture is proposed:

• Static region (shell): it is provided in the platform and it includes
  • PCIe XDMA interface
  • Master AXI interface
• Dynamic region (kernel)
  • A serial protocol IP (such as Aurora or GT Wizard) with streaming AXI interfaces
  • One 64-bit AXI master interface to transfer ingress data coming in through the transceivers
  • One 64-bit AXI slave interface to transfer egress data created by user in the host application (such as C++ codes)
  • One 64-bit scalar00 for user application to control (such as GT loopback) the kernel
  • One 32-bit scalar01 for the kernel to report back (such as link up) to the user application

To simplify the design, two 64-bit AXI streaming interfaces are used for the data transfer on the platform. If local memory is needed, DDR memory on the Alveo U200 card can be used with memory-mapped AXI interfaces and memory controller in the kernel.

Scalar registers are added in the kernel to facilitate direct access to the transceivers. Scalar00 is a 64-bit control register that drives the transceiver inputs. Scalar01 is a 32-bit status register that is driven by the transceiver outputs. The unused bits are reserved and can be used for additional control/status signals in the serial protocol IP if desired.

Xilinx’s new platform, Vitis (from Vivado version 2019.2 and later) is used to build a host application. The following instructions are based on Linux RedHat server with Alveo U200 XDMA platform.

Source Vivado 2019.2 (or later) and invoke Vitis technology in the Linux command prompt

<prompt> vitis &

Create your workspace, then click Launch

Select Create Application Project in the Welcome page

Name the new application project (for example, vitis_gt_kernel), then click Next

Select a platform for the project, then click Next

Select a template to create the project (Empty Application), then click Finish

After Vitis workspace GUI appears, select Xilinx tab, then click RTL Kernel Wizard

 RTL Kernel Wizard GUI will appear (depending on your system, it may take more than a minute) and there are 6 wizard pages

• Page 1: Welcome page, then click Next
• Page 2: General Settings, select the desired number of clocks and resets, then click Next

• Page 3: set scalar definition, then click Next

• Page 4: select number of AXI master interfaces and the names (this is for the global memory in the shell), then click Next

• Page 5: select the AXI4-Streaming interfaces (this example targets one master and one slave interface), then click Next

• Page 6: this is the summary page and it shows the function prototype of this kernel, this function will be incorporated into the Vitis  environment and is available for host application coding use (please note that the 2 AXI4-Streaming interfaces are not shown in the register map table because they are not mapped to the host memory), then click OK

• Vitis will complete the RTL Kernel Wizard and launch Vivado. This may take more than a minute

 A Vivado project of the kernel wizard is created and you can add the serial protocol IP and custom logic using the IP Catalog (RTL design flow) or the IP Integrator (IPI design flow)

Select desired Package Options, then click OK. When generation is complete, click Yes to exit Vivado. Click OK in the Vitis RTL Kernel import information pop-up window

After returning to Vitis project GUI, add the created hardware function, then click OK

The kernel design is now imported (shown in the src folder). You can select one of the 3 active build configuration options:

• Emulate-HW: hardware simulation
• Emulate-SW: software (faster than Emulate-HW)
• System: build hardware

Click the Project tab, then click Build Project to build the desired configuration

The above picture shows that Vitis generates the host_example.cpp (host application codes) and the user can modify to customize their test flow

The host example codes create a kernel, allocates memory for the scalars, AXI streams in the host, assign egress data to send to the GT kernel, reads ingress data from the GT kernel, and compare the read data with the initial data. The following code examples are taken from the example application and the user can modify the egress data assignments.

• Set arguments to the kernel function call

• Assign AXI4 streams: axis00 (master, ingress) and axis01 (slave, egress)

• Assign user data pattern to h_data (egress data)

• Kernel function call, and compare ingress data against user data pattern (h_data)

Run the application on the Alveo U200 card (the target platform) on server

The Vitis software platform provides an easy to understand design flow GUI to add a user kernel to a processor-based system. As FPGA becomes equipped with a hard processor(s), this design methodology enables users to customize the transceiver-based design.

With a pre-defined shell and kernel in the Vitis environment, users can create customized logic and data patterns in C-codes for design validation. This flow also provides a reference platform for FPGA logic designers who can create different kernels through the RTL Kernel Wizard. 

Alveo U200 Data Center Accelerator Card:

/content/xilinx/en/products/boards-and-kits/alveo/u200.html

Xilinx Runtime and Deployment Shell Download:

/content/xilinx/en/products/boards-and-kits/alveo/u200.html

UG1301 (Alveo Card Getting Started Guide):

/content/xilinx/en/support/documentation/boards_and_kits/accelerator-cards/2019_1/ug1301-getting-started-guide-alveo-accelerator-cards.pdf

Xilinx UltraScale and UltraScale+ Transceiver User Guides:

/content/xilinx/en/support/documentation/user_guides/ug578-ultrascale-gty-transceivers.pdf

/content/xilinx/en/support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf